FinFET ASIC Design

Taming the Complexity of FinFET ASIC Design

FinFET ASIC design involves the complex interaction of foundry process technology, IP design and integration, EDA tools and design methodologies, physical design, design for test, package design and product engineering. We focus on optimizing for the combination of power, performance, and area (PPA) appropriate for your device’s specific targets

  • We have access to the leading foundry process technologies to 7/14/16nm through our partnerships with the world’s leading-edge foundries.
  • In addition to our vast third-party IP portfolio, we provide custom logic, memory, analog and I/O solutions to meet your specific needs, be they targeted for high performance or low power. Our high-performance IP and I/O offering includes:
    • Ternary content-addressable memories (TCAMs)
    • Fast cache
    • Dense multi-port SRAMs
    • High-bandwidth memory (HBM2) PHY
    • High-bandwidth interconnect (HBI)
  • Our unique PPA-optimized design virtualization methodology is targeted to provide the best power, performance and area for your complex ASIC.

Rich design experience in FinFET ASICs

Through early R&D, our foundry partnerships and our cutting-edge customer base, we have been working in FinFET-class custom ICs and IP from the beginning and have emerged as a leader in the technologies required to design and manufacture a custom FinFET chip: 2.5D, HBM2, TCAM and FinFET-class IP platforms, as demonstrated by our recent tapeout for production of a 2.5D/HBM2 customer ASIC. Our FinFET ASIC design experience includes:

  • Large die at high performance (>1GHz), optimized for power
  • Up to reticle-sized devices and stitched interposers
  • High embedded SRAM content: 800Mb, custom SRAM, TCAM
  • 60+ designs with SerDes integration: Avago, Rambus, Snowbush, Cadence and Synopsys SerDes
  • Complex monolithic & 2.5D packaging

High-bandwidth, high-performance customer products enabled by eSilicon FinFET-class ASIC designs and IP

  • 100G/200G/400G Ethernet enterprise switches
  • Multi-terabit-class data center switches
  • Wireless backhaul GSN and NodeB controllers
  • Cognitive deep learning server accelerators
  • Edge aggregation and core service provider routers
  • Converged Ethernet networking adapters 10G/100GE
  • 100G metro and long-haul optical transport

eSilicon FinFET-class IP driving high-volume, high-performance ASICs

Market Tech IP Needs Optimization ASIC Benefit from eSilicon
IP Differentiation
Memory Subsystem Size
Networking 14/16 TCAM, HBM2, fast cache,
dense multi-port SRAM with
high throughput
Custom high-speed pseudo 2-port SRAM instances and asynchronous RFs Increase SRAM density by 14% and enabling asynchronous architecture porting and 2Gbps HBM 828Mb
Networking 7 TCAM, HBM2, fast cache,
dense multi-port SRAM with
high throughput
Ultra-high-speed memory optimization Increased speed by 20% and 2.5Gbps HBM 1.19Gb
Networking 14/16 High-bandwidth interconnect (HBI), UHS P2P, UHS TCAM, fast cache Custom HBI 16% reduction in unit price and  25% improvement in yield with
2.5Gbps+ HBI
Networking 14/16 2R/2W and 4R/4W RFs, HBM2 Custom 4R/4W instances Increased data throughput by 30% 856Mb
Machine Learning 28 TCAM, HBM Custom pseudo 2-port SRAM instances 2Gbps HBM and 1.0GHz TCAM
on 28nm
Machine Learning 14/16 HBM2, dense multi-port SRAM with high throughput Custom pseudo 2-port SRAM instances Increased storage capacity by 10% while saving 40% power ~2Gb

Please contact us at to find out more.