Mainstream ASICs

A Fast, Flexible Low-Risk ASIC Journey

eSilicon has been providing its customers a fast, flexible and low-risk path to production ASICs since 2000.  From concept to volume production, we deliver the right design support, IP, packaging and manufacturing technology. We focus on optimizing for the combination of power, performance, and area (PPA) appropriate for your device’s specific targets.

We have a proven track record in complex ASIC design, with over 98 percent first-time silicon success rate. We are a leading provider of SerDes and ARM core-based ASICs.

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Flexible engagement models to support every scenario

Whether it’s a full chip design or a GDSII handoff, eSilicon has an engagement model that will fit your needs.

We support our customers with comprehensive quality, product/foundry engineering, packaging and test engineering services – we’re there every step of the way from concept to volume production.

Design Tasks Spec RTL Netlist Placed gates GDS-II
Physical design Shared
Third-party IP
Package/2.5D/3D design
  • Our unique PPA-optimized design methodology is targeted to provide the best power, performance and area for your complex ASIC.
  • Our comprehensive partner network gives you the flexibility you need to get your design to market fast
  • Our extensive IP portfolio provides design support from 180nm to 7nm, including:
    • 58G long-reach SerDes
    • 112G long-reach SerDes
    • High-speed single-port ternary CAM (SP TCAM) compiler
    • High-speed single-port fast cache (FC) compiler
    • High-speed single-port (SP) SRAM compiler
    • High-density single-port (SP) SRAM compiler
    • High-speed dual-port (DP) SRAM compiler
    • High-speed 2-port asynchronous register file (2PARF) compiler
    • High-speed 2-port register file (2PRF) compiler
    • High-speed pseudo 2-port (P2P) SRAM compiler
    • Ultra-high-density (UHD) pseudo 2-port (P2P) SRAM compiler
    • High-speed pseudo 4-port (P4P) SRAM compiler
    • High-density 2-port asynchronous register file (2PARF) 1R1W latch-base compiler
    • High-density 3-port asynchronous register file (3PARF) 2R1W latch-base compiler
    • High-bandwidth interconnect (HBI™) + PHY for die-to-die interconnects
    • 1.8V oxide 1.8V LVDS I/O library
    • 1.8V oxide 1.8V/2.5V/3.3V general-purpose I/O library

Please contact us at to find out more. Or you can fill out a short ASIC project form to quickly get a quote on your ASIC.