Foundry engineering support provides safeguards for the high non-recurring engineering (NRE) cost of implementing new products. eSilicon provides the fab device and integration experience for first-time tapeout success. Tapeout support includes LVS (layout vs. schematic), DRC (design rule check), MEBES (manufacturing electronic beam exposure system) review and support, resulting in successful tapeouts.
Product engineering support safeguards product costs through effective yield management.
An experienced engineering team establishes baselines and maintains yield and performance targets. The baseline is established with product characterization which reduces production ramp risks. This baseline allows the team to efficiently root cause and troubleshoot deviations in production.
Investment in tools integrates data from all suppliers. These tools allow efficient, complete data analysis of complex tasks.
A review is performed during characterization to establish and optimize the baseline yield. This reduces production ramp risk by reviewing product stability across all corner extremes.
The yield is reviewed at both sort and final test. High and low VDD (supply voltage) testing is included as part of the standard production test program on corner lot testing across temperatures to cover the desired process/voltage/temperature (PVT) variables.
A parametric review across PVT is done to set and optimize product performance. All parameters are reviewed statistically using advanced tools to determine if adequate production margin exists to meet required performance targets. The fully data-logged units are archived for future debug reference.
The resulting characterization report, which includes both yield and parametric data, is used to set baseline expectations with subcontractors.
The yield targets are maintained through periodic reviews. We statistically review process WAT (wafer acceptance test), sort yield and final test yield data trends to continually optimize yield using a fully integrated yield management system. We also establish wafer yield rejection criteria with the fab early in the process to control both cost and quality.
We perform a variety of analyses to reduce the occurrence of random low-yield lots. Analysis may include:
Examples of wafer maps that may indicate fab issues
|Bull’s eye yield pattern||Doughnut yield pattern|
Examples of wafer maps that may indicate mask and probing test issues
|Reticle defect||Probing problem|