Media Coverage

September 18, 2017

Frenzy At 10/7nm

The focus is on cutting costs across the board, and it turns out there is still quite a bit to cut.
Semiconductor Engineering

September 8, 2017

The Engineering Long Game

Mentorship and Tackling the Continuing Education Conundrum
In this week’s episode of Fish Fry, we investigate the role of continuing education in our fast-paced electronic engineering ecosystem. Mike Gianfangna (eSilicon) joins us to discuss how both mentorship and formal education can help address the biggest challenges of chip design and why Mike feels that we should treat electronic design startups like wineries.
EE Journal Fish Fry

September 7, 2017

The Limits Of IP Reuse

The old model of write once, integrate many times doesn’t always work. Here’s why.
Semiconductor Engineering

August 10, 2017

IP Challenges Ahead

Part 2: For the semiconductor IP industry to remain healthy it has to constantly innovate, but it’s getting harder.
Semiconductor Engineering

August 2, 2017

AI ASICs Exposed!

These are ASICs, so who is sourcing the design? You need to look at who is really good at 2.5D integration and who owns the critical enabling IP for these designs (think the HBM2 physical interface and high-speed SerDes).
SemiWiki

July 31, 2017

The Secret Life Of Accelerators

Unique machine learning algorithms, diminished benefits from scaling, and a need for more granularity are creating a boom for accelerators.
Semiconductor Engineering

July 14, 2017

Is The IP Industry Healthy?

Part 1: IP has grown to become the largest segment of EDA revenue, but is it sustainable?
Semiconductor Engineering

June 29, 2017

Memories for the Internet

The growth in data rates, connected devices and address space – courtesy of IPv6 – are all creating an unprecedented need for optimized memory IP of all kinds.
SemiWiki

June 29, 2017

A Learning Machine For Machine Learning

Building the systems that power machine learning is an immensely complex task.
By Mike Gianfagna, eSilicon Vice President, Marketing
Semiconductor Engineering

June 19, 2017

Shrink Or Package?

Advanced packaging shifts to mainstream with complete flows, better tools, market proof points
Semiconductor Engineering

May 24, 2017

Reworking Established Nodes

Attention turns to pre-finFET processes because benefits of device scaling don’t apply equally to all markets.
Semiconductor Engineering

April 27, 2017

Historic FinFET/2.5D Firsts

Like the first trips to space, 2.5D design takes a lot of experimentation and practice.
By Mike Gianfagna, eSilicon Vice President, Marketing

Semiconductor Engineering

April 27, 2017

Why is TCAM Essential for the Cloud?

The use of ternary content-addressable memory (TCAM) is growing with the expansion of internet protocol for data driven by IoT and other data-intensive applications.
White paper by Dennis Dudeck, Field Applications Engineer, IP
& Lisa Minwell, Senior Director, IP Marketing, eSilicon
Semiconductor Engineering

April 27, 2017

Speeding Up Neural Networks

Adding more dimensions creates more data in neural networks, all of which needs to be processed using new architectural approaches.
Semiconductor Engineering

April 20, 2017

Moore’s Law: A Status Report

Part 1: The ability to shrink devices will continue for at least four more nodes as EUV begins to ramp, but it’s just one of a growing number of options, which include 2.5D/HBM ASICs.
Semiconductor Engineering

April 17, 2017

The Hunt for a Low-Power PHY

The physical layer interface is necessary for a chip to access the outside world, but it threatens to consume increasing portions of the power budget. What can be done to prevent a PHY limit?
Semiconductor Engineering

April 10, 2017

2.5D, FO-WLP Issues Come Into Focus

Advanced packaging goes mainstream, creating ripples throughout the back-end of the semiconductor industry.
Semiconductor Engineering

April 3, 2017

The Great Machine Learning Race

Chip industry repositions as machine learning technology begins to take shape; no clear winners yet.
Semiconductor Engineering

March 29, 2017

Custom Chip Verification Issues Grow

With the transition to finFETs, design conditions have grown more intense. They now include a wider PVT range and less headroom.
Semiconductor Engineering

March 28, 2017

Biz Talk: ASICs

Video interview with eSilicon CEO Jack Harding
Semiconductor Engineering

March 28, 2017

Optimal Memory Strategies: Where HBM2 Fits

As functionality increases in your ASIC, so does memory content. When is HBM2 technology the answer?
Whitepaper by Lisa Minwell, eSilicon Senior Director, IP Marketing

Semiconductor Engineering

February 25, 2017

Another Live Event at Samsung

Join eSilicon, Rambus and Samsung Foundry for an overview of the advanced technologies being deployed to address the challenges of FinFET-class ASIC designs.
SemiWiki

January 30, 2017

Rush Hour On The Technology Roadmap

ISSCC’s remarkable shift from technology-centric presentations to end user experiences signals a new chapter in our industry—one that puts the customer center stage, not the enterprise. This will bode well for dramatic semiconductor growth in the not-too-distant future.
By Mike Gianfagna, eSilicon Vice President, Marketing
Semiconductor Engineering