Media Coverage

October 3, 2018

Blog Review: Oct. 3

AI and the design ecosystem; new approach to 56G SerDes; handling counters in formal; changes for OSATs.
By Jesse Allen
Semiconductor Engineering

October 1, 2018

Using High-Bandwidth Memory

Tech Talk: Designing for high-throughput computing.
eSilicon’s Tim Horel talks about high-bandwidth memory Gen2 (HBM2), what engineers need to know to work with this technology, and how HBM2 integrates with ASICs at advanced nodes
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Video
By Ed Sperling

Semiconductor Engineering

September 27, 2018

56G 7nm SerDes: Eyewitness Account

The first public demonstration of a new 56G DSP-based SerDes IP block.
By Mike Gianfagna, eSilicon Vice President, Marketing
Semiconductor Engineering

September 21, 2018

Week In Review: Design, Low Power

eSilicon launched its new 7nm neuASIC IP platform for AI ASIC designs that need to adapt to changing AI algorithms.
By Jesse Allen
Semiconductor Engineering

September 20, 2018

Variation’s Long, Twisty Tail

Multiple sources of variability are causing unexpected problems in everything from AI chips to automotive reliability and time to market.
By Ed Sperling
Semiconductor Engineering

September 19, 2018

Semiconductor IP Reality Check

Beyond the IP working in silicon, does all the IP work well together? Before you bet the farm on your next 7nm design project, are you confident that all the IP will play well together?
By Daniel Nenni
SemiWiki

September 5, 2018

Processing In Memory

Growing volume of data and limited improvements in performance create new opportunities for approaches that never got off the ground.
By Ed Sperling
Semiconductor Engineering

September 5, 2018

The Ever-Changing ASIC Business

The ASIC business truly changed the world. Prior to this revolution, custom chips were only available to huge, integrated device manufacturers.
By Daniel Nenni
SemiWiki

August 30, 2018

Energy-Efficient AI

Building energy-efficient AI: Carlos Maciàn, senior director of innovation for eSilicon EMEA, talks about how to improve the efficiency of AI operations by focusing on the individual operations, including data transport, computation and memory.
Video
By Ed Sperling
Semiconductor Engineering

August 17, 2018

Measuring Up 7nm IP

The report spends some time reviewing eSilicon’s 7nm SerDes IP. This one IP block has become Star IP for many customers. It implements high-speed serial communication between chips and it’s performance is critical to achieving the overall throughput needed for advanced ASICs. 
By Daniel Nenni
SemiWiki

August 16, 2018

Big Shifts In Tech Conferences

New technologies and trends have created an explosion of shows; some attempt to go broad, others narrow and deep, with plenty of confusion all around.
By Ed Sperling and Katherine Derbyshire
Semiconductor Engineering

August 10, 2018

eSilicon and SiFive partner for next-generation SerDes IP

New SerDes must operate in a wide variety of system configurations — backplane configurations, temperature/humidity extremes, connector types. All this requires configuration of the SerDes equalization functions so the SerDes will match its operating environment so it can deliver the best power and performance. DSP-based SerDes can be “tuned” to the operating environment whereas analog SerDes cannot. 
By Daniel Nenni
SemiWiki

August 8, 2018

Designing custom chips in-house is the new normal

Cloud giants Amazon, Alibaba, Baidu, Facebook, Google, and Microsoft are now designing their own AI accelerator chips. Is this a fad or a short-term phase the cloud industry is going through? We believe that designing custom chips for specific tasks will become mainstream, in and out of the cloud. Few chip market segments will be immune. Processors, network switches, AI accelerators – all will be profoundly affected.
By Paul Teich
The Next Platform

August 2, 2018

More Sigmas In Auto Chips

The journey to autonomous cars is forcing fundamental changes in the way chips are designed, tested and tracked, from the overall system functionality to the IP that goes into those systems.
By Ann Steffora Mutschler
Semiconductor Engineering

July 30, 2018

High-Speed SerDes At 7nm

What’s changing inside of data centers and how does it affect chip design? eSilicon’s David Axelrad discusses the challenges of high-speed SerDes at 56Gbps and 112Gps, and why the switch from analog to digital is required for performance and low power.
Video
By Ed Sperling
Semiconductor Engineering

July 27, 2018

Pros, Cons Of ML-Specific Chips

Machine Learning’s Limits, Experts at the Table, part 3: Which processor type is the best for training and inferencing, and why are there so many companies trying to build new processors specifically for machine learning and AI?
By Ed Sperling
Semiconductor Engineering

July 26, 2018

Technical Conferences: The Insurmountable Opportunity

eSilicon’s Mike Gianfagna finds it increasingly difficult to choose between an expanding array of events tied to new markets, especially in artificial intelligence and machine learning.
By Mike Gianfagna, eSilicon Vice President, Marketing
Semiconductor Engineering

July 18, 2018

Networking-Optimized 7nm IP Platform

Hugh Durdan, VP, strategy & products, discusses eSilicon’s new networking-optimized 7nm IP platform. The platform includes 56G/112G SerDes, Ternary CAM, HBM2 PHY and more.
Video
ChipEstimate.com TV

July 17, 2018

Platform ASICs Target Datacenters, AI

There is a well-known progression in the efficiency of different platforms for certain targeted applications such as AI, as measured by performance and performance/Watt. At the low end are general-purpose CPUs, where the application is entirely in software, then GPUs, FPGAs, DSPs and finally custom hardware – an ASIC such as the Google TPU.
by Bernard Murphy
SemiWiki

July 17, 2018

5nm Design Progress

Improvements in power, performance and area are much more difficult to achieve, but solutions are coming into focus.
By Ann Steffora Mutschler
Semiconductor Engineering

July 9, 2018

A New ASIC for AI | eSilicon Launches neuASIC

The neuASIC platform for ASICs for AI is based upon a couple of different principles. The first is that machine learning algorithms are going to vary quite widely, while other important elements of the design will remain fixed.
By Bryon Moyer
Electronic Engineering Journal

July 9, 2018

Security Holes In Machine Learning And AI

A primary goal of machine learning is to use machines to train other machines. But what happens if there’s malware or other flaws in the training data?
By Ed Sperling
Semiconductor Engineering

July 6, 2018

What (Invisible) Dreams May Come

Carlos Macian, senior director, AI strategy and products, discusses eSilicon’s power and performance optimized machine learning/AI ASIC building blocks.
Audio
Fish Fry by Amelia Dalton
Electronic Engineering Journal

July 3, 2018

Machine Learning’s Limits

Machine Learning’s Limits, Experts at the Table, part 2: When machine learning errors occur, how and when are they identified and by whom?
By Ed Sperling
Semiconductor Engineering

July 2, 2018

The Darker Side Of Consolidation

What happens when companies are combined? The outcome often isn’t as good as the announcement.
By Ed Sperling
Semiconductor Engineering

June 29, 2018

Week In Review: Design, Low Power

eSilicon adds configurable 7nm IP platform; EDA in the Cloud; Portable Stimulus 1.0; building SoCs with AI; NetSpeed uncorks AI-powered platform; Moortec unveils embedded monitoring system.
By Jesse Allen
Semiconductor Engineering

June 28, 2018

New 7nm IP Platform for Data Center ASICs

Meeting the power, performance and density requirements of advanced networking-class ASICs is a significant challenge for system OEMs. The only thing that can be said for creating such a design, “throwing it over the wall” to an ASIC vendor, and then hoping to receive a production-ready device a couple of months later is that you are blessed with an optimistic nature.
By Max Maxfield
EEWeb

June 28, 2018

FinFET ASICs: It Takes A Platform

In order to minimize time to market, you must avoid distractions from your one true mission – developing that core element of the chip that will make your product truly different.
By Mike Gianfagna, eSilicon Vice President, Marketing
Semiconductor Engineering

June 27, 2018

7nm IP platform for networking and data center applications

Hugh Durdan, VP, strategy & products, discusses eSilicon’s new highly configurable 7nm IP platform, which delivers a complete ecosystem of networking-optimized IP, including 56G/112G SerDes, TCAM, HBM2 PHY, specialty memories, I/Os.
Video
Design & Reuse

June 26, 2018

Plug & Play 7nm Networking IP Platform

Hugh Durdan, VP, strategy & products, discusses eSilicon’s new 7nm IP platform. All IP in the platform is plug and play, using the same metal stack, reliability requirements, operating ranges, control interfaces and DFT methodology.
Video
ChipEstimate.com TV

June 26, 2018

7nm Networking Platform Delivers Data Center ASICs

All the elements of the platform have configurability built in, making it easier to perform the balancing act required to hit the power, performance and area requirements for advanced networking applications.
By Daniel Nenni
SemiWiki

June 14, 2018

Near-Threshold Issues Deepen

Process variation plus timing are adding to low-power challenges at the most advanced nodes.
By Ann Steffora Mutschler
Semiconductor Engineering

June 8, 2018

The Week In Review: Design

Machine learning for signoff; last level cache; AI platform; SoftBank sells 51% stake in Arm China, but not source code.
By Jesse Allen
Semiconductor Engineering

June 7, 2018

Machine Learning’s Limits

Machine Learning’s Limits, Experts at the Table, part 1: Why machine learning works in some cases and not in others.
By Ed Sperling
Semiconductor Engineering

June 6, 2018

AI Comes to ASICs in Data Centers

A novice AI ASIC designer could be advised to lean on someone like eSilicon just as Nervana did. After all, the ASIC expert could give some comfort and solid technology foothold in AI ASICs backed by its own real-world experience.
By Junko Yoshida
EE Times

June 6, 2018

Being Intelligent about AI ASICs

eSilicon just announced an offering they call neuASIC that promises to give developers of AI ASICs much more flexibility, potentially huge gains in power efficiency and performance, and a well-thought-out methodology for implementation.
By Tom Simon
SemiWiki

June 5, 2018

Neural ASIC platform promises easy AI integration

The neuASIC platform is what independent IP provider eSilicon presents as a fundamentally new approach to building application-specific integrated circuits (ASICs) for artificial intelligence /neural network applications.
By Julien Happich
eeNews Europe

June 4, 2018

FPGAs Becoming More SoC-Like

“For AI, FPGAs are always going to be constrained both in capacity and performance, so you will not be able to really get to production-level specs with an FPGA. You can play with it and group things, but ultimately you’re going to have to get to an ASIC.”
By Ann Steffora Mutschler
Semiconductor Engineering

April 26, 2018

Deep Learning And The Future

Why are great strides in artificial intelligence and deep learning happening now?
By Mike Gianfagna, eSilicon Vice President, Marketing

Semiconductor Engineering

April 26, 2018

More Nodes, New Problems

Acceleration of advanced processes, skyrocketing complexity and cost, and concerns about IP availability are raising some difficult questions.
Semiconductor Engineering

April 2, 2018

How To Choose The Right Memory

Different memory types and approaches can have a big impact on cost, power, bandwidth and latency.
Semiconductor Engineering

March 26, 2018

When AI Goes Awry

So far there are no tools and no clear methodology to eliminating bugs. That would require understanding what an AI bug actually is.
Semiconductor Engineering

March 22, 2018

Applying Machine Learning To Chips

Goal is to improve quality while reducing time to revenue, but it’s not always so clear-cut.
Semiconductor Engineering

March 22, 2018

Deep Learning Market Forces

Managing the massive amounts of data generated today won’t come cheap.
By Mike Gianfagna, eSilicon Vice President, Marketing
Semiconductor Engineering

March 15, 2018

AI: The Next Big Thing

And it’s going to push the limit on semiconductor design, manufacturing and packaging.
Semiconductor Engineering

February 16, 2018

What does a Deep Learning Chip look like

Chips targeted at deep learning applications are often not “chips” at all using the traditional definition of a monolithic piece of silicon in a package. Rather, deep learning chips are combinations of monolithic chips and massive external memories all integrated in a sophisticated 2.5D package. The use of 2.5D makes the whole process a good bit more complex but allows the delivery of significant new capabilities.
By Daniel Nenni
SemiWiki

February 13, 2018

Go Big Or Go Home — Why eSilicon Went Big

Advanced communications, networking and machine learning accelerator systems all need complex chip designs and many times off-the-shelf chips aren’t sufficient. 
Forbes

January 8, 2018

Getting Serious About Chiplets

Issues involving known good die and test still remain, but the chiplet approach is getting a lot of interest.
Semi Engineering