Ngoài ra, trong khuôn khổ STEMCON 2019, còn có các hoạt động triển lãm sản phẩm khoa học – công nghệ; trao Giải thưởng Pearson về Đổi mới Phương pháp Giảng dạy cho Giảng viên; Học bổng cho Nữ Sinh viên trong ngành STEM của eSilicon.
The Future Digital Workforce: Implications and Opportunities in STEM In addition, within the framework of STEMCON 2019, there are also exhibitions of scientific and technological products; the Pearson Award for Innovation in Teaching Methods for Teachers; and the eSilicon Scholarship for Female Students in the STEM industry.
Every year, 3D InCites recognizes company and individual contributions to the development of the heterogeneous roadmap, including 3D packaging, interposer integration, advanced fan-out wafer-level packaging, MEMS and sensors, and full system integration, via their 3D InCites awards program.
Mentor IC Design Blog
An eSilicon 7nm DSP SerDes generates PRBS-31, 56 Gbps PAM4 signals; the signals are routed from the eSilicon test-board via Samtec Bulls Eye High-Performance Test System cable assemblies. The 1.02e-11 BER, which is several orders of magnitude better than the spec, is nearly error free, even pre-FEC. By Danny Boesing
Samtec Blog | Video
A new report from The Linley Group, “A Guide to Processors for Deep Learning,” analyzes deep-learning accelerators and IP cores for artificial intelligence, neural networks, and vision processing for inference and training. Many new companies and products target this fast-growing market, which topped $4 billion in chip revenue in 2018.
Carlos Macián, eSilicon’s senior director of AI strategy and products, talks about how to utilize memory differently and reduce the movement of data in AI chips, and what impact that has on power and performance. By Ed Sperling
Semiconductor Engineering | Video
High-speed serial links are critical for the next generation of servers, switches, routers and 5G infrastructure. White paper by Kar Yee Tang, Senior Product Marketing Manager, eSilicon
Networking Intellectual Property (IP) developer Precise-ITC and ASIC and IP provider eSilicon today announce a partnership to produce an integrated multi-rate, multi-channel 400G Ethernet test chip. MarketWatch
With or without new leading-edge microprocessors, the demand for faster compute, bigger storage and speedier networks continues to grow. As this year’s conference will show, the industry keeps coming up with new ways to deliver. By John Morris
eSilicon was in the Samtec booth at DesignCon 2019 presenting their collaboration with Wild River Technology to develop an advanced test system that addresses the difficult signal integrity demands of 56/112G PAM4 operation. The test system design utilizes the upcoming IEEE P370 standard in association with compliance metrics 802.3bs, OIF CEI – 56G PAM4, and COBO to validate the required performance. By Pat Hindle
Signal Integrity Journal
Designing SerDes for 56G and 112G is complex and challenging. In fact, there are only a few companies with working silicon. eSilicon is one of them and made an announcement at DesignCon this year that highlights another huge challenge for these designs – how to test them and measure their performance. By Tom Simon
Optimizing complex chips, particularly AI chips and some advanced SoCs, requires decisions about overall system architecture, and memory is a key variable. By Ann Steffora Mutschler
A chip may work, but it’s only successful if it performs in the context of the delivered system, and that takes a village. By Mike Gianfagna, eSilicon Vice President, Marketing Semiconductor Engineering
Our instant gratification society continues to crave more data and higher speeds. This transition is further fueled by other trends like AI, smart cities, autonomous vehicles and surveillance technology. What do we do? We continue to innovate. White paper by Kar Yee Tang, Senior Product Marketing Manager, eSilicon
ChipEstimate.com Tech Talk
Experts at the Table, Part 2: What’s needed to make different packaging approaches more affordable, and why that may not be a critical factor in the short-term. By Ed Sperling