The CEO Outlook lineup includes Ed Sperling, editor in chief of Semiconductor Engineering, who will serve as moderator. Panelists will be John Chong, vice president of product and business development for Kionix, Jack Harding, president and CEO of eSilicon, John Kibarian, PDF Solutions’ president and CEO, and Wally Rhines, CEO emeritus of Mentor, a Siemens Business. by Bob Smith
eSilicon taped out a 7nm test chip to validate the latest release of the neuASIC IP platform, a library of IP that supports a wide range of functions found in artificial intelligence applications.
eSilicon also taped out a 7nm test chip to provide silicon validation of its PHY to support the new HBM2E JEDEC standard, JESD235B. The 7nm test chip, which includes a controller from Northwest Logic, will be part of a 2.5D test system to verify end-to-end support for the new HBM interfaces. By Jesse Allen
The big news here is that eSilicon is committing to move ALL ASIC and IP design to the Google Cloud Platform (GCP). They have been operating in a hybrid cloud environment for about a year and a half and now they are taking the next big step. Most of the chip design cloud activity today is hybrid so eSilicon is blazing trails here. By Daniel Nenni
eSilicon taped out a 7nm test ASIC that supports 400G gearbox and retimer functionality. The test ASIC includes four lanes of eSilicon’s long-reach 112 Gbps SerDes and eight lanes of its long-reach 56 Gbps SerDes, integrated with media access control (MAC), forward error correction (FEC) and gearbox IP from Precise-ITC. By Jesse Allen
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A major shift in the application-specific integrated circuit (ASIC) market has occurred over the past five years. The forces at play are most evident at the top end of the market, but they will impact the entire customer base and supply chain over time. By Jack Harding, eSilicon President and CEO
Once IP quality and standards support are ascertained, the integration challenges begin. Things like metal stack, design for test, reliability, control interfaces, and operating range all matter, and inconsistencies create challenges. By Ann Steffora Mutschler
eSilicon Corporation migrated to Google Cloud Platform and Elastifile to create a scalable solution that’s capable of powering the processing and resource-intensive steps of semiconductor design.
Google Cloud Customer Case Studies
Leveraging the TSMC and Synopsys VDE collaboration, several partners and customers have accelerated their move to the cloud and have successfully completed designs on the cloud. eSilicon has been using their Synopsys-based implementation flow to build complex IP on the cloud targeting TSMC’s advanced technologies.
During the SoC Design Session at the recent Linley Spring Processor Conference in Santa Clara, Carlos Macian, senior director AI strategy and products at eSilicon, held a talk entitled “Opposites Attract: Customizing and Standardizing IP Platforms for ASIC Differentiation.” by Camille Kokozaki
Experts at the Table, part 1: Shrinking features isn’t enough anymore. The big challenge now is how to achieve economies of scale and minimize complex integration issues.
By Ed Sperling
The increase in global internet traffic, along with decentralization of cloud and data centers, has driven wired and wireless networks to support 5G network infrastructures. 5G technology promises to enable 1,000 times more traffic, 10 times faster speed, and a 10 times increase in throughput. By Teddy Lee, Architect SI/PI, eSilicon
ANSYS Advantage Magazine
Ngoài ra, trong khuôn khổ STEMCON 2019, còn có các hoạt động triển lãm sản phẩm khoa học – công nghệ; trao Giải thưởng Pearson về Đổi mới Phương pháp Giảng dạy cho Giảng viên; Học bổng cho Nữ Sinh viên trong ngành STEM của eSilicon.
The Future Digital Workforce: Implications and Opportunities in STEM In addition, within the framework of STEMCON 2019, there are also exhibitions of scientific and technological products; the Pearson Award for Innovation in Teaching Methods for Teachers; and the eSilicon Scholarship for Female Students in the STEM industry.
Every year, 3D InCites recognizes company and individual contributions to the development of the heterogeneous roadmap, including 3D packaging, interposer integration, advanced fan-out wafer-level packaging, MEMS and sensors, and full system integration, via their 3D InCites awards program.
Mentor IC Design Blog
An eSilicon 7nm DSP SerDes generates PRBS-31, 56 Gbps PAM4 signals; the signals are routed from the eSilicon test-board via Samtec Bulls Eye High-Performance Test System cable assemblies. The 1.02e-11 BER, which is several orders of magnitude better than the spec, is nearly error free, even pre-FEC. By Danny Boesing
Samtec Blog | Video
A new report from The Linley Group, “A Guide to Processors for Deep Learning,” analyzes deep-learning accelerators and IP cores for artificial intelligence, neural networks, and vision processing for inference and training. Many new companies and products target this fast-growing market, which topped $4 billion in chip revenue in 2018.
The Linley Group
Carlos Macián, eSilicon’s senior director of AI strategy and products, talks about how to utilize memory differently and reduce the movement of data in AI chips, and what impact that has on power and performance. By Ed Sperling
Semiconductor Engineering | Video
High-speed serial links are critical for the next generation of servers, switches, routers and 5G infrastructure. White paper by Kar Yee Tang, Senior Product Marketing Manager, eSilicon
Networking Intellectual Property (IP) developer Precise-ITC and ASIC and IP provider eSilicon today announce a partnership to produce an integrated multi-rate, multi-channel 400G Ethernet test chip. MarketWatch
With or without new leading-edge microprocessors, the demand for faster compute, bigger storage and speedier networks continues to grow. As this year’s conference will show, the industry keeps coming up with new ways to deliver. By John Morris
eSilicon was in the Samtec booth at DesignCon 2019 presenting their collaboration with Wild River Technology to develop an advanced test system that addresses the difficult signal integrity demands of 56/112G PAM4 operation. The test system design utilizes the upcoming IEEE P370 standard in association with compliance metrics 802.3bs, OIF CEI – 56G PAM4, and COBO to validate the required performance. By Pat Hindle
Signal Integrity Journal
New SerDes test system design utilizes the upcoming IEEE P370 standard in association with compliance metrics 802.3bs, OIF CEI – 56G PAM4, and COBO to validate the required performance.
By Patrick Hindle
Signal Integrity Journal
Designing SerDes for 56G and 112G is complex and challenging. In fact, there are only a few companies with working silicon. eSilicon is one of them and made an announcement at DesignCon this year that highlights another huge challenge for these designs – how to test them and measure their performance. By Tom Simon
Optimizing complex chips, particularly AI chips and some advanced SoCs, requires decisions about overall system architecture, and memory is a key variable. By Ann Steffora Mutschler
A chip may work, but it’s only successful if it performs in the context of the delivered system, and that takes a village. By Mike Gianfagna, eSilicon Vice President, Marketing Semiconductor Engineering
Our instant gratification society continues to crave more data and higher speeds. This transition is further fueled by other trends like AI, smart cities, autonomous vehicles and surveillance technology. What do we do? We continue to innovate. White paper by Kar Yee Tang, Senior Product Marketing Manager, eSilicon
ChipEstimate.com Tech Talk
Experts at the Table, Part 2: What’s needed to make different packaging approaches more affordable, and why that may not be a critical factor in the short-term. By Ed Sperling