eSilicon announces 7nm FinFET ASIC design win
High-speed networking ASIC based on complete TSMC 7nm IP platform
SAN JOSE, Calif. — January 9, 2018 — eSilicon, an independent provider of FinFET-class ASIC design, custom IP and advanced 2.5D packaging solutions, today announced its first 7nm design win at a major OEM. The design win follows eSilicon’s development of a complete IP platform on TSMC 7nm process technology for high-bandwidth networking, high-performance computing and AI applications. The 7nm IP platform includes a 56G long-reach SerDes, TCAM, HBM2 PHY, high-speed fast cache, single-port and dual-port SRAMs and many high-speed, high-density multi-port memory architectures.
The design win was enabled by the power and performance profile of TSMC’s 7nm process technology. As compared to TSMC’s 16FF+ technology, 7nm provides a 35% speed gain at the same power or 60% power reduction at the same speed. These factors helped to address the demanding requirements of this advanced data center chip.
“Advanced data center chips consistently push the envelope for higher performance at lower power,” said Jack Harding, president and CEO of eSilicon Corporation. “TSMC’s 7nm technology provided the right balance of power reduction and performance improvement to address these demands.”
eSilicon is an independent provider of complex FinFET-class ASIC design, custom IP and advanced 2.5D packaging solutions. Our ASIC+IP synergies include complete, 2.5D/HBM2 and TCAM platforms for FinFET technology at 14/16/7nm as well as SerDes, specialized memory compilers and I/O libraries. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets.
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