eSilicon at TSMC OIP 2017
High-Performance 7FF IP Platform and 7FF HBM2/LL HBM Combo PHY
For release on September 6, 2017, San Jose, Calif.
eSilicon, an independent provider of FinFET-class ASIC design, custom IP and advanced 2.5D packaging solutions, will deliver several presentations in booth 807 at the 2017 TSMC OIP Ecosystem Forum in Santa Clara, California at the Santa Clara Convention Center on September 13, 2017.
High-Performance Networking and Computing 7FF IP Platform
Highly differentiating TCAM and memory compilers, I/O libraries and 56G SerDes for high-performance, high-bandwidth applications.
8:30 AM & 12:40 PM, booth 807
7FF Combo PHY: High-Bandwidth Memory Gen2 and Low-Latency HBM
Complete 2.5D FinFET solution for HBM2 and low-latency HBM.
10:20 AM and 3:10 PM, booth 807
eSilicon is an independent provider of complex FinFET-class ASIC design, custom IP and advanced 2.5D packaging solutions. Our ASIC+IP synergies include complete, silicon-proven 2.5D/HBM2 and TCAM platforms for FinFET technology at 14/16nm. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets.
Collaborate. Differentiate. Win.™
eSilicon is a registered trademark, and the eSilicon logo and Collaborate. Differentiate. Win. are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.