TIRIAS research publishes white paper on ASIC market
Cites eSilicon capabilities for complex FinFET ASIC designs
SAN JOSE, Calif. — January 23, 2018 — eSilicon, an independent provider of FinFET-class ASIC design, custom IP and advanced 2.5D packaging solutions, today announced the availability of a white paper from TIRIAS Research that examines today’s market dynamics driving leading-edge ASIC design and manufacturing. The paper reviews the requirements for these ASIC designs and the associated business models. TIRIAS Research was able to talk to a number of eSilicon customers and other system designers to get a perspective on the options available to startups and established system companies for building these chips.
TIRIAS Research is a high-tech research and advisory firm. They provide custom research and advisory services on technologies, markets, and ecosystems to a select group of technology industry leaders. Kevin Krewell, the author of the white paper, is principal analyst at TIRIAS Research. He is focused on computing industry challenges, including AR/VR, autonomous machines, connectivity, CPU architecture, gaming, graphics, machine learning, and security. He has more than 30 years of industry experience in both engineering and marketing.
“This was a unique opportunity to get an insider perspective on what’s driving leading-edge ASIC design,” said Krewell. “Even though we needed to anonymize the identities of the interviewees to protect confidentiality, the key requirements of the market and eSilicon’s abilities to address those requirements came through.”
“It was a rewarding experience working with Kevin and the TIRIAS team on this project,” said Mike Gianfagna, vice president of marketing at eSilicon. “The organization has tremendous reach in our marketplace and that made a big difference in the quality of the research.”
The white paper is available from TIRIAS Research free of charge and may be accessed by visiting the TIRIAS Research website.
eSilicon is an independent provider of complex FinFET-class ASIC design, custom IP and advanced 2.5D packaging solutions. Our ASIC+IP synergies include complete, 2.5D/HBM2 and TCAM platforms for FinFET technology at 14/16/7nm as well as SerDes, specialized memory compilers and I/O libraries. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets.
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