FinFET-Class ASICs:
Taming Complexity Through Collaboration

The explosion of data generated, moved, stored and analyzed around the world today has changed custom IC development forever. The massive, FinFET-class ASICs used in today’s networking, data center, artificial intelligence (AI) and 5G infrastructure applications require doing things in silicon that have never been done before.

eSilicon manages the design, development and manufacturing of highly complex ASICs for our customers. To meet the demands of building these monster ASICs, we have created a new model for taking our ASIC customers from RTL to volume production: transparent, collaborative, flexible.

Complexity changes everything

Working sequentially—throwing your ASIC design over the wall to your ASIC supplier and getting your production-ready chip a few months later—doesn’t work anymore. When you are pushing technology to the limit, everything is so interrelated, it requires the right team in place from the start of the ASIC engagement. Our new ASIC model is a holistic, collaborative approach to reduce risk and improve efficiency.

Transparent, collaborative, flexible

Our new model focuses on making the chip design process transparent, collaborative and flexible by starting with a complete team: ASIC customer, ASIC supplier, IP ecosystem and key supply chain members. This brings the broadest set of expertise to the program and allows our customers to become deeply involved in making IP and supply chain choices that best fit their programs. We define this as the coASIC model as described in our white paper The CoASIC Business Model – From Closed to Collaborative. Please contact us at to request the white paper.

  • Transparency. eSilicon keeps an open line of communication with the team in terms of price, program status, technical details, risks and mitigation.
  • Collaboration. Team members work to their strengths:
  • Critical IP: IP requirements are addressed as a team to identify best-in-class choices.
  • Problem resolution: Advanced designs mean at least one aspect has never been done before. The question is not IF there are challenges, but HOW they are managed. We approach problem solving as a shared activity among all stakeholders.
    Our patented knowledge base and optimization technology are critical to identifying design challenges early as well as in supporting problem resolution.
  • Flexibility. We are independent and support multiple advanced FinFET foundries and an extensive IP ecosystem. Our customers choose what works for them. They aren’t forced into a pre-determined, one-size-fits-all set of technology and IP.

Offerings and customer markets

Our ASIC solutions offering provides ASIC design, development and production management services to help you implement your ASIC and choose the optimal third-party or custom IP for your design. Then we manage your ASIC through test and yield to predictable, on-time device delivery in volume. We work with best-in-class supply chain partners in design services, design tools, semiconductor IP, manufacturing, test, and package/assembly.

Our custom and off-the-shelf IP offerings support our ASIC customers as well as stand-alone IP engagements. We supply a wide array of 7nm-180nm silicon-proven memories and I/O libraries, including ternary content-addressable memory (TCAM) and HBM2 PHY.

Our ASIC+IP synergies include complete, silicon-proven 2.5D/HBM2 solutions for FinFET technology.

Our customers are semiconductor companies, integrated device manufacturers (IDMs), OEMs and wafer foundries that sell their products into a variety of end markets, including networking, computing, AI and 5G infrastructure.

Patented knowledge base and optimization technology

The number of variables a design team must consider has exploded: foundries, technologies, process variants and more. It’s impossible to evaluate all the possible combinations manually. We have developed a knowledge base and optimization technology that we use to help us create world-class, complex, differentiated chips. It is built on collective knowledge from over 300 tapeouts and over 3,000 quotes. This technology gives us “peripheral vision” – we can see all possible configurations in terms of the many variables that go into a custom IC and pick the best options for your chip. We use this technology to:

  • Meet all market requirements – performance, power, area (PPA), schedule, yield and cost
  • Optimize the complete design – memory as well as logic
  • Analyze a very broad spectrum of variables, much broader than the solution space considered by traditional design methods
  • Evaluate all possible IP configurations

We define our methodology as “design virtualization.” For more information, please download our design virtualization white papers: Design Virtualization and Its Impact on SoC Design and Design Virtualization Technology For Low-Power ASICs.

Collaborate. Differentiate. Win.

Please contact us at to find out more.