IP, Methodology and Expertise

The right blend of technology and experience, delivered in a well-orchestrated fashion, creates winning opportunities

Building FinFET-class systems-in-a-package is a daunting task. The demands of the high-performance networking, computing, 5G infrastructure and AI markets are un-forgiving when it comes to schedule and performance. Getting that all-important system chip right requires the best IP assembled the right way by the right team.

But winning in your market requires so much more. It’s all about predictability and risk reduction.

IP: from best-in-class to platform predictability

Reliable, silicon-proven IP that delivers the needed functionality and performance is a given for any chip design project. But more is required to achieve a winning formula. Will the IP work together in the final design? Things like control interfaces, metal stack and testability strategies can cause tapeout delays and impact final performance.

At eSilicon, we’ve addressed the problem directly with our IP platforms. Collections of IP that are designed to work together predictably and reliably. We apply the same stringent rules to third-party IP that is part of the platform. And we build in application-specific configurability as well to allow you to hit your power, performance and area targets more reliably. We offer IP platforms for high-performance networking and AI/machine learning applications.

eSilicon’s IP platform concept
eSilicon’s IP platform concept

Methodology: robust, predictable and intelligent

Design methodology is no longer only about chip design. Advanced semiconductor technology is now delivered as a system-in-package, often containing multiple devices integrated on an interposer. A winning design methodology must not only consider chip design, but the way the chip interacts with the package and the way the package interacts with the system.

Introducing StarDesigner™, eSilicon’s chip-package-system design flow. StarDesigner coordinates all aspects of the design process, from floor-planning to chip assembly, package/substrate design, package-level test to system-level integration. We also employ machine learning technology to optimize the entire process.

StarDesigner capabilities include:

  • Support for 7nm FinFET ASIC, interposer and 2.5D package design
  • Chip-package-system concurrent design that reduces time-to-market and improves quality
  • Extensive knowledge base ensures exceptional power, performance and area for the most advanced designs
  • Integrated approach reduces the risks associated with manufacturability and yield for complex system-in-package designs
  • Hosted on a hybrid on-premise/cloud infrastructure with machine learning technology for maximum efficiency

Experience: deep expertise with a collaborative culture

eSilicon delivers design and manufacturing expertise across the globe. Our distributed team provides deep domain expertise with a local presence, thanks to our cloud-enabled design infrastructure.

eSilicon’s global presence: US, Spain, Italy, Romania, China, Vietnam and Malaysia
eSilicon’s global presence: US, Spain, Italy, Romania, China, Vietnam and Malaysia

Out team covers all aspects of ASIC design, from RTL to tapeout including package/interposer design, power and signal integrity. Our support doesn’t stop at tapeout. We also provide complete logistics and supply chain management to deliver the final chip in volume, including test development, test bring-up, characterization, qualification, supply chain management and quality.

We are an experienced FinFET-class team with reticle-sized devices and stitched interposers. We have delivered over 300 tapeouts with over a half billion units shipped. We also have extensive experience with SerDes-based designs on over 60 tapeouts. There are over 300 engineers developing IP for memories/specialty libraries, I/Os, SerDes, and PHYs at eSilicon.

Our culture is one of collaboration with our customers. We support many handoff models and we maintain a highly interactive design program with our customers and suppliers to ensure all design and manufacturing challenges are addressed quickly and with high quality.

eSilicon’s design DNA

Holistic

Lean

Rigorous

Proactive

  • System-level view for SiP/MCM
  • End-to-end & 360º
  • Integrated & cross-functional
  • Flat organization
  • Quick escalation path for efficient decision-making
  • Step-by-step audits
  • Quality gates between phases
  • Engage early
  • Design exploration up front
  • Check continuously

Collaborative

Flexible

Transparent

Automated

  • On-site support
  • Architectural consulting
  • Product ownership
  • Many handoff models, spec to GDSII
  • IP selection
  • Multiple supply chain partners
  • Subject matter experts involved in your ASIC development
  • Online project management with 24/7 reporting
  • Memory abstraction, optimization & instantiation
  • Feedthrough detection, analysis & insertion
  • Automatic floorplan creation & analysis
  • STA partitioning
  • Automatic design kit creation & update
  • Automated technology analysis
  • Automatic auditing & baselining
  • Version control for scripts, IP, databases

Collaborate. Differentiate. Win.

Please contact us at sales@esilicon.com to find out more.