The explosion of data generated, moved, stored and analyzed around the world today has changed custom IC development forever. The massive, FinFET-class ASICs used in today’s networking, data center, artificial intelligence (AI) and 5G infrastructure applications require doing things in silicon that have never been done before.
eSilicon manages the design, development and manufacturing of highly complex ASICs for our customers. To meet the demands of building these monster ASICs, we have created a new model for taking our ASIC customers from RTL to volume production: transparent, collaborative, flexible.
Working sequentially—throwing your ASIC design over the wall to your ASIC supplier and getting your production-ready chip a few months later—doesn’t work anymore. When you are pushing technology to the limit, everything is so interrelated, it requires the right team in place from the start of the ASIC engagement. Our new ASIC model is a holistic, collaborative approach to reduce risk and improve efficiency.
Our new model focuses on making the chip design process transparent, collaborative and flexible by starting with a complete team: ASIC customer, ASIC supplier, IP ecosystem and key supply chain members. This brings the broadest set of expertise to the program and allows our customers to become deeply involved in making IP and supply chain choices that best fit their programs. We define this as the coASIC model as described in our white paper The CoASIC Business Model – From Closed to Collaborative. Please contact us at firstname.lastname@example.org to request the white paper.
Our ASIC solutions offering provides ASIC design, development and production management services to help you implement your ASIC and choose the optimal third-party or custom IP for your design. Then we manage your ASIC through test and yield to predictable, on-time device delivery in volume. We work with best-in-class supply chain partners in design services, design tools, semiconductor IP, manufacturing, test, and package/assembly.
Our custom and off-the-shelf IP offerings support our ASIC customers as well as stand-alone IP engagements. We supply a wide array of 14/16nm-180nm silicon-proven memories and I/O libraries, including ternary content-addressable memory (TCAM) and HBM2 PHY.
Our customers are semiconductor companies, integrated device manufacturers (IDMs), OEMs and wafer foundries that sell their products into a variety of end markets, including networking, computing, AI and 5G infrastructure.
The number of variables a design team must consider has exploded: foundries, technologies, process variants and more. It’s impossible to evaluate all the possible combinations manually. We have developed a knowledge base and optimization technology that we use to help us create world-class, complex, differentiated chips. It is built on collective knowledge from over 300 tapeouts and over 3,000 quotes. This technology gives us “peripheral vision” – we can see all possible configurations in terms of the many variables that go into a custom IC and pick the best options for your chip. We use this technology to:
We define our methodology as “design virtualization.” For more information, please download our design virtualization white papers: Design Virtualization and Its Impact on SoC Design and Design Virtualization Technology For Low-Power ASICs.
Please contact us at email@example.com to find out more.