High-Bandwidth Memory PHY & 2.5D Solutions

Expand System Performance: 7nm, 14/16nm, 28nm Hardened HBM2/HBM2E/LL HBM PHY & 2.5D Solutions for TSMC and Samsung

System Integration: Complete HBM Interface

Since 2011, eSilicon has been conducting research to develop products and processes that deliver a complete HBM solution. With production 2.5D packaged silicon, eSilicon offers a unique and powerful advantage, delivering the next step in integration, cost reduction, and system power management while increasing and integrating system bandwidth via HBM. Our end-to-end HBM solution includes 2.5D ecosystem management, the PHY, ASIC design, systems in package (SiP) design, manufacturing, assembly and test. Through an external partnership, we offer a complete HBM interface including both the controller and the PHY, which is silicon validated in an integrated system that includes the interposer and DRAM stack.

High-bandwidth memory achieves higher bandwidth while using less power in a substantially smaller form factor than DDR4 or GDDR5. At 14/16nm, HBM addresses the bandwidth gap with up to 256 GB/s data rate per memory at 2Gbps pin speed.

At 7nm, the pin speed increases to 3.2Gbps with bandwidth up to 307GB/s. The HBM2 PHY interface features eight independent channels using a total of 1024 data pins. With support for 2, 4, or 8 HBM2 stacks, the density of signals, coupled with interposer design, requires careful design, thorough timing analysis and validation. eSilicon’s HBM2 PHY is a complete, validated hardened IP that is ready for chip integration.

eSilicon also provides a 7nm combo PHY supporting HBM2E, HBM2 and low-latency HBM (LL HBM). With 7nm HBM2E, the pin speed increases to 3.2Gbps with bandwidth up to 409.6GB/s.

Low-Latency HBM Support

eSilicon’s 7nm combo HBM PHY supports the newly announced low-latency high-bandwidth DRAM memory (LL HBM) from Renesas.

Low-latency HBM offers a unique set of benefits for computing, networking and AI application such as:

  • High-speed random access and small data granularity, providing a significant advantage in accessing small random data
  • Memory access to focus area only, offering an effective use of memory bandwidth, quick transfer to the processor and small bus power
  • Simple protocol and memory controller, saving expensive processor real estate and featuring processor pipeline-friendly design
  • High temperature profile with a Tjmax of 115C to help solve thermal and package challenges while enabling closer proximity to the processor

eSilicon will provide a demonstration board to enable testing and validation of its combo HBM PHY with the memory controller and the DRAM stack. Contact your eSilicon sales person directly or sales@esilicon.com.

Learn more about Renesas low-latency HBM.

HBM2 SoC Subsystem Benefits:

  • Fully hardened 28/16/14/7nm HBM2/HBM2E/LL HBM PHY for easy integration
  • Production-ready design available for licensing: first 7nm product already taped out
  • Fifth generation of HBM PHYs proven in silicon across multiple foundries and technology
  • Interposer design available for faster time to market
  • Maximum data rate supported across all timing corners
  • HBM2E at 3.2Gbps taped out in 7nm technology
  • Full productization support available: signal integrity, power integrity and thermal analysis


The  HBM2 PHY has been developed to the JEDEC JESD 235A specification. It has been developed on 28/16/14/7nm. The HBM2E PHY has been developed to the JEDEC JESD 235A & JESD 235B specification on TSMC N7 technology.

At 7nm, the PHY supports up to 409.6Gbytes/sec bandwidth with 8x128b channels at 3.2Gbps per I/O.

The HBM2 PHY is DFI 4.0 compliant with several controller-independent features such as:

  • READ/WRITE/CK strobe training
  • READ leveling training
  • I/O calibration
  • Lane repair
  • Independent programmable control/status registers (CSRs) via APB or IEEE1500 interface
  • Low-power mode through APB interface
  • MISR test


PHY Feature Specification
Data Rate 0.5-3.2Gbps per I/O
Channels 8 independent channels
Self-Refresh Supported through memory controller
I/O per Channel 212
Bandwidth per Stack Up to 409.6GB/s
Data I/O 128 per channel, 8 channels and 16 pseudo channels
ECC ECC and parity support in conjunction with the controller. (ECC on DM signals)
Data Byte Invert (DBI) DBI supported in conjunction with the controller
Data Mask (DM) DM supported in conjunction with the controller
RAS Support RAS supported in conjunction with the controller
Cycles/Command 1 cycle (exception is Row Activate at 2 cycles) per JEDEC specification
Interoperability Testing Supports any third-party DFI 4.0-compliant memory controller vendor
IEEE1500 Support Separate IEEE1500 port for direct access to the memory stack and PHY
Impedance Calibration Sharing Self-contained calibration per PHY instance across all eight channels
Related Signal Pass-Through Provides ability for signals not related to PHY to be passed through between DRAM stack and ASIC core
Power-Down Modes IDDQ MODE and dynamic power-down of receivers during WRITE
Functional Temperature Range (Tj) -40C to 125C

7FF Integrated I/O

At 7nm the I/O supports up to 3.2Gbps DDR operation across a 4mm interposer channel.

  • Clock speeds up to 1.6Ghz
  • Calibrated output current programmable
  • Junction operating temperature -40˚C to 125˚C
  • Complies with ESD requirements
  • Supports flip-chip assembled SoC device, I/O interfaces to a micro-bump technology

Interposer Design

Silicon interposers provide an optimal integration platform:

  • Excellent thermal expansion matching
  • Increased signal speed due to shorter interconnects with a smaller form factor
  • Reduced RLC parasitics, power and ESD requirements

This silicon interposer technology platform is based on several enabling process modules and unit process capabilities. eSilicon can develop your customized interposers.

eSilicon interposer design and implementation capabilities:

  • Through-silicon via (TSV) system design and wiring analysis
  • TSV assembly (chip-to-wafer bonding, temporary bonding/debonding, etc.)
  • Ultra-thin wafer back-grinding and polishing
  • Signal and power integrity analysis and IC-to-TSV optimization
  • Process design kit (PDK) and EDA flow set-up
  • Reliability and failure analysis

Detailed Information

Licensing, front-end views, silicon quality results, white papers or complete data sheets, are available from sales@esilicon.com. Additional features and benefits for eSilicon’s 7nm IP platform are available under NDA. Contact sales@esilicon.com.

Online Access

All eSilicon IP is available in IP Navigator at https://star.esilicon.com, our online IP exploration tool. Navigator provides access to eSilicon’s full portfolio of IP products. Memory instances may be generated, analyzed and downloaded. Power, performance, and area (PPA) data is pre-loaded for easy data comparison and analysis.


White Papers

  • The New Deep Learning Memory Architectures You Should Know About | eSilicon
  • Supercharge Your Applications with Samsung High-Bandwidth Memory | Samsung Memory
  • Multi-Die Packaging and Thermal Superposition Modeling | Amkor, eSilicon & Samsung Foundry for Semitherm 2018
  • Start Your HBM/2.5D Design Today | eSilicon, SK Hynix, Amkor Technology, Northwest Logic and Avery Design Systems

Videos & Webinar Replays


  • 7FF IP platform for networking, high-performance computing, AI & 5G
  • 14LPP IP platform for networking, high-performance computing, AI & 5G
  • Ternary CAMs (TCAMs)
  • 28/16/14/7nm HBM2/HBM2E/LL HB PHY