Need lower power? Need more bandwidth? eSilicon has complete high-bandwidth memory (HBM2) solutions from PHY IP, ASIC, interposer and package design through manufacturing. Take advantage of HBM2 integrated with 2.5D technology to address your power and bandwidth requirements.
High-bandwidth memory achieves higher bandwidth while using less power in a substantially smaller form factor than DDR4 or GDDR5. At 14/16nm, HBM addresses the bandwidth gap with up to 256 GB/s data rate per memory at 2Gbps pin speed. At 7nm, the pin speed increases to 2.4Gbps with bandwidth up to 307GB/s. The HBM2 PHY interface features eight independent channels using a total of 1024 data pins. With support for 2, 4, or 8 HBM2 stacks, the density of signals, coupled with interposer design, requires careful design, thorough timing analysis and validation. eSilicon’s HBM2 PHY is a complete, validated hardened IP that is ready for chip integration.
eSilicon’s 2.5D/HBM2 is first to production with a comprehensive 2.5D solution that includes eSilicon’s HBM2 PHY, interposer and systems in package (SiP) design; volume manufacturing, assembly and test; and complete 2.5D/HBM ecosystem management.
The HBM2 PHY has been developed to the JEDEC HBM2 standard. It has been developed on TSMC 7FF, Samsung 14LPP, TSMC 16FF+ GL, and TSMC 28HPC technologies.
The HBM PHY is DFI 4.0 compliant with several controller-independent features such as:
|Data Rate||0.1-2.4Gbps per I/O|
|Channels||8 independent channels|
|Self-Refresh||Supported through memory controller|
|I/O per Channel||212|
|Channel Bandwidth||Up to 307GB/s|
|Data I/O||128 per channel, 8 channels and 16 pseudo channels|
|ECC||ECC and parity support in conjunction with the controller. (ECC on DM signals)|
|Data Byte Invert (DBI)||DBI supported in conjunction with the controller|
|Data Mask (DM)||DM supported in conjunction with the controller|
|RAS Support||RAS supported in conjunction with the controller|
|Cycles/Command||1 cycle (exception is Row Activate at 2 cycles) per JEDEC specification|
|Interoperability Testing||Supports any third-party DFI 4.0-compliant memory controller vendor|
|IEEE1500 Support||Separate IEEE1500 port for direct access to the memory stack and PHY|
|Impedance Calibration Sharing||Self-contained calibration per PHY instance across all eight channels|
|Related Signal Pass-Through||Provides ability for signals not related to PHY to be passed through|
|Power-Down Modes||IDDQ MODE and dynamic power-down of receivers during WRITE|
|Temperature Range (Tj)||-40C to 125C|
|Voltage Level Target||VDD (logic supply) at circuit: 0.675V -> 0.99V
I/O supply voltage – at die level 1.2V (+/-5%)
The I/O supports up to 2.4Gbps DDR operation across a 4mm interposer channel.
Since 2011, eSilicon has been conducting research to develop products and processes that deliver a complete HBM solution. With production 2.5D packaged silicon, eSilicon offers a unique and powerful advantage, delivering the next step in integration, cost reduction, and system power management while increasing and integrating system bandwidth via HBM. Our end-to-end HBM solution includes 2.5D ecosystem management, the PHY, ASIC design, SiP design, manufacturing, assembly and test. Through our partnership with Northwest Logic, we offer a complete HBM interface including both the controller and the PHY, which is silicon validated in an integrated system that includes the interposer and DRAM stack.
Silicon interposers provide an optimal integration platform:
This silicon interposer technology platform is based on several enabling process modules and unit process capabilities. eSilicon can develop your customized interposers.
eSilicon interposer design and implementation capabilities:
Please contact eSilicon at email@example.com for more information, silicon quality results, white papers or data sheets.
All eSilicon IP is available in IP Navigator at https://star.esilicon.com, our online IP exploration tool. Navigator provides access to eSilicon’s full portfolio of IP products. Memory instances may be generated, analyzed and downloaded. Power, performance, and area (PPA) data is pre-loaded for easy data comparison and analysis.
Our HBM2 webinars and white paper, co-authored with SK Hynix, Amkor Technology, Northwest Logic and Avery Design Systems, are available at our Start Your HBM2/2.5D Design Today web page.
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