IP for High-Bandwidth Applications

With the increasing number of Internet-connected consumer devices, manufacturing systems, business tools, customer service appliances, medical equipment, agricultural sensors and other devices, the difference between required and available bandwidth is becoming huge. High-speed, high-bandwidth networking enables the aggregation, automation and analysis of this data.

eSilicon specializes in high-performance, high-bandwidth IP + 2.5D solutions that target networking, high-performance computing, artificial intelligence (AI) and 5G wireless infrastructure applications. Memory and I/O products in this category include long-reach SerDes, ternary content addressable memory (TCAMs), fast cache, multi-port and asynchronous register files and HBM2 PHY.

Our silicon-proven 14/16nm specialized memories provide 2.5GHz worst-case operation with more than a billion searches per second along with the 2.5D integration of 1024 Gbytes/sec data rate high-bandwidth memory (HBM2).

eSilicon also offers high-performance and high-bandwidth IP and 2.5D solutions on 7nm technology that target networking and high-performance computing applications. They include 3.3GHz caches, TCAMs with up to 1.8 billion searches per second (worst-case operation), and the 2.5D integration of up to 1228 Gbytes/sec data rate high-bandwidth memory (HBM2).

Front-end views of our 7nm IP offering are available now by contacting sales@esilicon.com.


A serializer/deserializer (SerDes) is an IC transceiver that converts parallel data to serial data and vice-versa. SerDes is used in very high-bandwidth, high-speed applications such as computing, networking, AI & 5G infrastructure. Our SerDes team is now working on a 56G long-reach SerDes in 7nm technology. Architectural work on a 112G design has begun as well.

High-Bandwidth Memory

HBM2 achieves higher bandwidth while consuming less power in a substantially smaller form factor than DDR4, or GDDR5. At 14/16nm, HBM2 addresses the bandwidth gap with up to 256 GB/s data rate per memory at 2Gbps pin speed. At 7nm, the pin speed increases to 2.4Gbps with bandwidth up to 307GB/s.  The HBM2 PHY interface features eight independent channels using a total of 1024 data pins. With support for 2, 4, or 8 HBM2 stacks, the density of signals, coupled with interposer design, requires careful design, thorough timing analysis and validation. eSilicon’s HBM2 PHY is a complete, validated hardened IP that is ready for chip integration.

eSilicon’s 2.5D/HBM2 is first to production with a comprehensive 2.5D solution that includes eSilicon’s HBM2 PHY, interposer  and systems in package (SiP) design; volume manufacturing, assembly and test; and complete 2.5D/HBM ecosystem management.


Memory processing tends to be the bottleneck in network performance. If memory cannot keep up with increasingly fast processors, the processors have to wait, stalling the system. Specialty memories address the problem in a variety of ways. Ternary content-addressable memories (TCAMs) are unique ─ they search an entire lookup table in one cycle. eSilicon’s ternary CAM compiler provides up to 2.5 billion search results in one second (GSPS), enabling high-efficiency, cost-effective solutions for applications such as network search engines, cache for network processors, QoS services, classifications, Ethernet, ATM switches and other diverse networking applications.

Fast Cache

eSilicon has designed custom high-speed single-port cache memories that are optimized to meet the high-performance requirements of industry-standard processor cores. Our 14LPP high-speed single-port fast cache compiler is part of our complete 14LPP IP platform. eSilicon’s new 7FF fast cache compiler offers speeds up to 3.3 GHz.

Multi-Port Register File & Asynchronous Register File

eSilicon has designed four-port register file memory compilers and asynchronous register file memory compilers catering to multiple customers in the networking and communications domains. The four-port memories have two write ports and two read ports. The asynchronous memories have one synchronous write port and one asynchronous read port.

Networking IP Platforms

14LPP Products Key Feature
High-speed SP TCAM 1.2GHz
Ultra-high-speed SP TCAM 1.5GHz
High-speed SP fast cache 2.5GHz
High-speed DP SRAM
High-speed pseudo 2-port SRAM 1.2GHz
High-density pseudo 2-port SRAM
High-density 2-port asynchronous RF Async READ
Ultra-high-speed pseudo 2-port SRAM 1.5GHz
High-speed four-port register file
1.8V oxide 1.8V/2.5V/3.3V general-purpose I/O library
1.8V oxide 1.8V LVDSOUT I/O library
1024-bit HBM2 PHY 2Gbps per bit
7FF Products Feature
56G long-reach SerDes
1024-bit HBM2 PHY
High-speed single-port ternary CAM (SP TCAM) 1.8GHz performance
High-speed single-port fast cache (FC) > 3GHz performance
High-speed single-port (SP) SRAM
High-speed dual-port (DP) SRAM simultaneous read/write operations
High-speed 2-port asynchronous register file (2PARF)
High-speed pseudo 2-port (P2P) SRAM 1.8GHz performance
Ultra-high-density (UHD) pseudo 2-port (P2P) SRAM 900MHz performance
High-speed pseudo 4-port (P4P) SRAM 2R/2W
High-speed pseudo quad-port (PQP) SRAM
1.8V oxide 1.8V LVDS I/O library
1.8V oxide 1.8V/2.5V/3.3V general-purpose I/O library

Contact & Online Access

Please contact us at sales@esilicon.com for more information, silicon quality results, white papers or complete data sheets.

All eSilicon IP is available in IP Navigator at https://star.esilicon.com, our online IP exploration tool. Navigator provides access to eSilicon’s full portfolio of IP products. Memory instances may be generated, analyzed and downloaded. Power, performance, and area (PPA) data is pre-loaded for easy data comparison and analysis.


Additional details can be found in our TCAM brochure.

Our newest HBM white paper, co-authored with SK Hynix, Amkor Technology, Northwest Logic and Avery Design Systems, is available online: Start Your HBM/2.5D Design Today.

You may also be interested in our  Advanced ASIC Video Series:

  • What is High-Bandwidth Memory (HBM2) and 2.5D Packaging?
  • What is a TCAM?
  • Where is a TCAM Used in an ASIC?