58G & 112G PAM4 & NRZ DSP-Based Long-Reach SerDes Family in 7nm

Enabling Next-Generation Servers, Switches, Routers and 5G Infrastructure

Networking systems are becoming increasingly complex. Meeting the power, performance and density requirements of advanced networking-class ASICs is a significant challenge for system OEMs. Next-generation 12.8, 25.6 and 51.2Tb/s switches and routers demand extreme flexibility in system architecture, greater I/O bandwidth and power scaling to achieve the required performance and density.

Key challenges facing network architects are:

  • The number of SerDes lanes is approaching 300
  • System power is exploding, sometimes reaching over 400W
  • Legacy backplanes have high insertion loss, limiting the maximum throughput

The SerDes family is a critical piece of eSilicon’s 7nm IP platform that provides a complete ecosystem of networking-optimized, highly configurable IP. All of the IP in the platform are “plug and play,” using the same metal stack, reliability requirements, operating ranges, control interfaces and DFT methodology. This configurability and compatibility results in better performance, higher density and faster time to market.

At the core of the 7nm IP platform is eSilicon’s SerDes technology which delivers a new level of performance and versatility and is based on a novel DSP-based architecture. Two 7nm SerDes support 58G and 112G NRZ/PAM4 operation to provide the best power efficiency for server, switches and routers. The architecture delivers unprecedented power efficiency for a true long-reach capability, with hole-free operation down to 1.25Gb/s. The clocking architecture provides extreme flexibility to support multi-link and multi-rate operations per SerDes lane. A multitude of protocols are supported including a variety of Ethernet standards (from 1000Base to 400G Base) and Fibre Channel. The architecture also allows further reductions in power consumption for shorter-reach channels.

Enabling Next-Gen 25.6 and 51.2Tb/s Switches, Routers and 800G Systems

Unique Benefits of eSilicon’s 7nm 58G/112G SerDes Family

  • Unprecedented power efficiency for 58G and 112G applications
  • Optimized form factor for networking applications
  • Programmable to enable the best power and reach trade-offs for a given application
  • First-to-market full DSP (Tx and Rx) 58G SerDes in 7nm with true long-reach performance for use in the most challenging backplane applications
  • Maximum clocking flexibility – hole-free down to 1.25Gb/s
  • Long and short channel support
  • Design flexibility through a unique clocking architecture and firmware-controlled design
  • User-centric experience for greater ease of use, bring-up and validation


  • Reduce time to market with our revolutionary graphical user interface (GUI) that allows quick, easy bring-up and system validation. From the GUI, users can access all the monitoring features such as non-destructive eye diagrams, SNR & BER, bathtubs, histograms and power measurements
  • Error-free 58G PAM4 operation over a 30dB backplane without FEC
  • 112G solution based on 58G silicon-proven architecture (recognized as best in class by multiple tier-one customers)
  • Microprocessor-enabled link monitoring including channel impulse response and error histogram
  • Self-calibrated architecture with optimized power/performance trade-offs
  • Multiple operational modes to support reference and reference-less applications
  • Wide variety of IEEE and OIF-standardized protocols including Ethernet and Fibre Channel
  • Supports multiple IEEE and OIF-standardized protocols, such as Ethernet, CPRI/eCPRI and Fibre Channel
  • A single evaluation module (EVM) kit test environment for the 58G/112G SerDes family: same test boards, same GUI, same user-friendly experience from 58G to 400G
eSilicon full DSP SerDes Receive Eye Diagram
Automatically generated 7nm 58G DSP SerDes receive eye diagram

ASIC & SerDes Expertise

Our new SerDes family was developed by a world-class SerDes team with over 15 years of proven experience in networking, including two 28nm silicon-proven 56G SerDes implementations. The new SerDes family leverages the same architecture plus some unique features derived from eSilicon’s long-standing experience integrating complex SerDes into bleeding-edge networking ASICs.

eSilicon/Wild River Technology 56G SerDes evaluation board
eSilicon & Wild River Technology advanced SerDes test system

In addition to outstanding performance and versatility, eSilicon’s SerDes family provides a new level of user experience for the ASIC design and signal integrity communities. Leveraging a decade of experience integrating complex SerDes into networking ASICs, eSilicon incorporated this unique knowledge into its new 7nm SerDes family. The result is a new-to-the-market, customer-centric SerDes that is easy to integrate and easy to use.

Reach Beyond the Rack

Our true long-reach DSP-based SerDes coupled with Samtec’s low-loss Twinax Flyover Cable Assembly enables reach beyond the rack: seven meters (23 feet) and beyond for data centers and 5G wireless infrastructure, an industry first.

Samtec Seven-Meter ExaMAX Backplane Cable Assembly
Seven-meter (23-foot) Samtec ExaMAX® Backplane Cable Assembly

Detailed Information

Additional features and benefits for eSilicon’s SerDes family and the rest of the 7nm IP platform are available under NDA.

You can schedule a demonstration of the 58G SerDes test chip by contacting your eSilicon sales representative directly or via sales@esilicon.com. EVM kits (demo boards and related software/firmware) are also available for customer evaluation via sales@esilicon.com.