56G & 112G PAM4 & NRZ SerDes Family in 7nm

Enabling Next-Generation Servers, Switches and Routers

Networking systems are becoming increasingly complex. Meeting the power, performance and density requirements of advanced networking-class ASICs is a significant challenge for system OEMs. Next-generation 12.8, 25.6 and 51.2Tb/s switches and routers demand extreme flexibility in system architecture, greater I/O bandwidth and power scaling to achieve the required performance and density.

Key challenges facing network architects are:

  • The number of SerDes lanes is approaching 300
  • System power is exploding, sometimes reaching over 400W
  • Cooling becomes increasingly difficult and expensive, especially on the fabric cards
  • Legacy backplanes have high insertion loss, limiting the maximum throughput

The SerDes family is a critical piece of eSilicon’s 7nm IP platform that provides a complete ecosystem of networking-optimized, highly configurable IP. All of the IP in the platform is “plug and play,” using the same metal stack, reliability requirements, operating ranges, control interfaces and DFT methodology. This configurability and compatibility results in better performance, higher density and faster time to market.

At the core of the 7nm IP platform is eSilicon’s SerDes technology which delivers a new level of performance and versatility and is based on a novel DSP-based architecture. Two 7nm PHYs support 56G and 112G NRZ/PAM4 operation to provide the best power efficiency for server, switches and routers. The architecture delivers unprecedented power efficiency for a true long-reach capability, with hole-free operation down to 1Gb/s. The clocking architecture provides extreme flexibility to support multi-link and multi-rate operations per SerDes lane. A multitude of protocols are supported including a variety of Ethernet standards and Fibre Channel. The architecture also allows further reductions in power consumption for shorter-reach channels.

Enabling Next-Gen 25.6 and 51.2Tb/s Switches, Routers and 800G Systems

Unique Benefits of eSilicon’s 7nm 56G/112G SerDes Family

  • Unprecedented power efficiency for 56G and 112G applications
  • Optimized form factor for networking applications
  • Programmable to enable the best power and reach trade-offs for a given application
  • Maximum clocking flexibility – hole-free down to 1Gb/s
  • Long and short channel support
  • User-centric experience for greater ease of use, bring-up and validation

Features

  • Microprocessor-enabled link monitoring including channel impulse response and error histogram
  • Self-calibrated architecture with optimized power/performance trade-offs
  • Multiple operational modes to support reference and reference-less applications
  • Wide variety of IEEE and OIF-standardized protocols including Ethernet and Fibre Channel

ASIC & SerDes Expertise

Our new SerDes family was developed by a world-class SerDes team with over 12 years of proven experience in networking, including two 28nm silicon-proven 56G SerDes implementations. The new SerDes family leverages the same architecture plus some unique features derived from eSilicon’s long-standing experience integrating complex SerDes into bleeding-edge networking ASICs.

SerDes test photo

Silicon-proven SerDes architecture

In addition to outstanding performance and versatility, eSilicon’s SerDes family provides a new level of user experience for the ASIC design and signal integrity communities. Leveraging a decade of experience integrating complex SerDes into networking ASICs, eSilicon incorporated this unique knowledge into its new 7nm SerDes family. The result is a new-to-the-market, customer-centric SerDes that is easy to integrate and easy to use.

Detailed Information

Additional features and benefits for eSilicon’s SerDes family and the rest of the 7nm IP platform are available under NDA.

You can schedule a demonstration of the 56G SerDes test chip by contacting your eSilicon sales representative directly or via sales@esilicon.com.