FinFET ASICS targeting the high-performance computing, networking, AI & 5G infrastructure markets require critical differentiating IP that is focused on the specific needs of the chip and market. The IP that defines system performance and capability includes on-board memory, the HBM interface and SerDes technology. eSilicon now offers all this IP, built to the needs of our customers.
ASIC designs targeted at applications such as high-bandwidth networking, high-performance computing, AI and 5G infrastructure typically require high-performance serializer/deserializer, or SerDes capability to compensate for the limited number of input/output pins on the chip. These designs also typically utilize high-bandwidth memory (HBM) stacks that are interfaced to the ASIC through a 2.5D package.
eSilicon has successfully taped out over 60 customer designs that integrate advanced SerDes technology from our network of IP partners. We are now building our own SerDes technology to ensure we can meet customer requirements, on time and in spec.
Our growing SerDes design team has extensive experience in analog, mixed-signal, and SerDes designs having successfully proven two 56G SerDes architectures in silicon at 28nm. This team is now working on a 56G long-reach SerDes in 7nm technology. Architectural work on a 112G design has begun as well.
We will be announcing more technical details and availability soon.