Ternary CAM
Ternary and Binary Content-Addressable Memory Compilers
eSilicon® embedded binary and ternary content addressable memories (BCAMs and TCAMs) have been provided to networking customers for over 15 years, helping these customers meet the demand for wire-speed packet processing, access control lists and other requirements of high-bandwidth delivery. eSilicon binary and ternary CAMs are available in geometries from 7nm to 180nm.
High-Performance, High-Density Embedded CAM Compilers for Network Applications
eSilicon offers a broad range of feature-rich, high-performance, high-density embedded BCAM and TCAM compilers. Our binary and ternary CAM compilers provide high-efficiency, cost-effective solutions for applications such as network search engines, cache for network processors, QoS services, classifications, Ethernet, ATM switches and other diverse networking applications.
User-Selectable Features
In addition to a full set of standard features, our TCAM and BCAM compilers provide a comprehensive set of user-selectable features that are chosen at compile time. Customers can choose just the features that they need for a specific application to optimize performance, power or area (PPA).
- Priority encoder
- Redundancy
- Partial-pipelined search
eSilicon CAM designs are available in 7nm to 180nm geometries, optimized to meet challenging PPA requirements of IDM and leading foundry processes. We can supply ternary CAM instances or compilers to fit the number of instances required.
Features
- Patented Duo architecture for extreme area and power reduction
- Multiple architectures available in 7nm, 10nm, 14nm, 16nm, 28nm, 40nm, 65nm, 90nm, 130nm and 180nm
- Flexible selection of width and depth with up to 1K entries and 160Kb macro size
- Easily cascadable to increase search depth without degradation in performance
- Single-cycle search, read and write operations
- Smart Power Management and partial-pipelined search for reduced power
- Fast cycle and access time: the 7nm TCAM offers more than a 50% increase in performance compared to previous FinFET generations
- Valid-bit, global and local valid-bit reset
- Match-in and match-out flag for each entry
- Flexible masking (bit/group/global)
- Hand-crafted layout for high density and high performance
Detailed Information
Front-end views, silicon quality results, white papers or complete data sheets, are available from sales@esilicon.com. Additional features and benefits for our 7nm TCAM and the rest of eSilicon’s 7nm IP platform are available under NDA. Contact sales@esilicon.com.
Online Access
All eSilicon IP is available in IP Navigator at https://star.esilicon.com, our online IP exploration tool. Navigator provides access to eSilicon’s full portfolio of IP products. Memory instances may be generated, analyzed and downloaded. Power, performance, and area (PPA) data is pre-loaded for easy data comparison and analysis.
Resources
White Papers
- The New Deep Learning Memory Architectures You Should Know About | eSilicon
- Supercharge Your Applications with Samsung High-Bandwidth Memory | Samsung Memory
- Multi-Die Packaging and Thermal Superposition Modeling | Amkor, eSilicon & Samsung Foundry for Semitherm 2018
- Start Your HBM/2.5D Design Today | eSilicon, SK Hynix, Amkor Technology, Northwest Logic and Avery Design Systems
Videos & Webinar Replays
- ASICs Unlock Deep Learning Webinar | Amkor, eSilicon, Northwest Logic & Samsung Memory
- HBM2/2.5D/SerDes FinFET ASICs on 14nm Webinar | Samsung, ASE Group, eSilicon, Northwest Logic & Rambus
- What is High-Bandwidth Memory (HBM2) and 2.5D Packaging?
- What is a TCAM?
- Where is a TCAM Used in an ASIC?
Brochures:
- 7FF IP platform for networking, high-performance computing, AI & 5G
- 14LPP IP platform for networking, high-performance computing, AI & 5G
- Ternary CAMs (TCAMs)
- 28/16/14/7nm HBM2 PHY
