Ternary CAM
Ternary and Binary Content-Addressable Memory Compilers
eSilicon® embedded binary and ternary content addressable memories (BCAMs and TCAMs) have been provided to networking customers for over 15 years, helping these customers meet the demand for wire-speed packet processing, access control lists and other requirements of high-bandwidth delivery. eSilicon binary and ternary CAMs are available in geometries from 7nm to 180nm.
High-Performance, High-Density Embedded CAM Compilers for Network Applications
eSilicon offers a broad range of feature-rich, high-performance, high-density embedded BCAM and TCAM compilers. Our binary and ternary CAM compilers provide high-efficiency, cost-effective solutions for applications such as network search engines, cache for network processors, QoS services, classifications, Ethernet, ATM switches and other diverse networking applications.
User-Selectable Features
In addition to a full set of standard features, our TCAM and BCAM compilers provide a comprehensive set of user-selectable features that are chosen at compile time. Customers can choose just the features that they need for a specific application to optimize performance, power or area (PPA).
- Priority encoder
- Redundancy
- Partial-pipelined search
eSilicon CAM designs are available in 7nm to 180nm geometries, optimized to meet challenging PPA requirements of IDM and leading foundry processes. We can supply ternary CAM instances or compilers to fit the number of instances required.
Features
- Patented Duo architecture
- Multiple architectures available in 7nm, 10nm, 14nm, 16nm, 28nm, 40nm, 65nm, 90nm, 130nm and 180nm
- Flexible selection of width and depth
- Up to 160Kb compiled
- Up to 1K entries and up to 160 bits per word
- Easily cascadable to increase search depth without degradation in performance
- Single-cycle search, read and write operations
- Smart Power Management and partial-pipelined search for reduced power
- Fast cycle and access time: the 7nm TCAM delivers 1.8 GSPS worst case and up to 2.5 GSPS under typical conditions
- Valid-bit, global and local valid-bit reset
- Match-in and match-out flag for each entry
- Flexible masking (bit/group/global)
- Hand-crafted layout for high density and high performance
Availability
| Process | Status |
|---|---|
| 7nm FF | Front-end views available |
| 14nm LPP | Available |
| 16nm FFC | Available |
| 16nm FF+GL | Available |
| 16nm FF+LL | Available |
| 28nm HPM | In production |
| 40nm LP | In production |
| 40nm G | In production |
| 55nm LP | In production |
| 65nm GP | In production |
| 90nm G | In production |
| 110nm G | In production |
| 130nm G | In production |
| 180nm G | In production |
Contact & Online Access
Please contact us at sales@esilicon.com for more information, silicon quality results, white papers or complete data sheets.
All eSilicon IP is available in IP Navigator at https://star.esilicon.com, our online IP exploration tool. Navigator provides access to our full portfolio of IP products. Memory instances may be generated, analyzed and downloaded. Power, performance, and area (PPA) data is pre-loaded for easy data comparison and analysis.
Resources
Additional details can be found in our TCAM brochure.
Our newest HBM white paper, co-authored with SK Hynix, Amkor Technology, Northwest Logic and Avery Design Systems, is available online: Start Your HBM/2.5D Design Today.
You may also be interested in our Advanced ASIC Video Series:
- What is High-Bandwidth Memory (HBM2) and 2.5D Packaging?
- What is a TCAM?
- Where is a TCAM Used in an ASIC?
