FinFET-Class 14/16nm IP Platforms

Advanced IP for Advanced Technologies:
eSilicon has SRAM and TCAM on 14/16nm FinFET

eSilicon is offering eFlex™ SRAMs and register files and eFlexCAM™ ternary content-addressable memories (TCAMs) in Samsung 14LPP and TSMC 16FF process variants.

14LPP Networking and High-Performance Computing IP Platform

The silicon-proven 14LPP networking and high-performance computing IP platform is available now. This IP platform has been designed specifically to meet the high-speed and high-bandwidth requirements of Asics and ASSPs targeted for networking and high-performance computing applications. The platform includes the following IP:

  • High-speed and ultra-high-speed single-port ternary CAM compiler (SP TCAM)
  • High-speed and ultra-high-speed pseudo two-port (P2P) SRAM compiler
  • High-speed dual-port (DP) SRAM compiler
  • High-speed single-port fast cache (SP FC) compiler
  • High-density two-port asynchronous register file (2PARF) compiler
  • High-density pseudo two-port (P2P) SRAM compiler 1.8V oxide 1.8V/2.5V/3.3V general-purpose I/O library
  • 1.8V oxide 1.8V LVDSOUT I/O library
  • 1024 bit HBM2 PHY

High-Bandwidth Memory

High-bandwidth memory Gen2 (HBM2) achieves higher bandwidth while consuming less power in a substantially smaller form factor than DDR4, GDDR5 or Hybrid Memory Cube (HMC). This technology addresses the bandwidth gap with 1024Gbytes/sec data rate with four HBM stacks in a package. HBM2 has eight independent channels using a total of 1024 input and output pins. This density of signals, coupled with interposer design, requires careful design and thorough timing analysis. eSilicon has designed IP and systems in package (SiP), manufactured, assembled and tested systems that include HBM2 as well as 2.5D packaging.


The HBM2 PHY is JEDEC JESD235A compliant. The PHY supports up to 256Gbytes/sec bandwidth with 8x128b channels at 2Gbps per I/O. The PHY is DFI 4.0 compliant with several controller-independent features, including:

  • Plug & play: with hard macro and built-in clock control there’s no lengthy timing closure and physical design
  • Custom design for optimized timing and area
  • Rich set of built-in features
  • Flexible: minimum dependence on controller features
  • Signal integrity: custom routing scheme used on interposer to significantly minimize crosstalk and skew
  • Maximum timing margin: PHY includes training, calibration and VREF programmability features
  • DFI and IEEE1500 compliant
  • APB interface enables CPU override of built-in training, repair and calibration

14/16nm TCAM Memory Compilers

The TCAM is an excellent choice for packet forwarding and classification in internet routers as well as in a variety of other applications that require high-speed table lookup. eSilicon’s TCAM provides performance of 2.5 billion searches per second (BSPS) under typical operating conditions with overdrive voltage and a latency of 1-2 clock cycles. TCAM performance is 1.25 giga searches per second (GSPS) under worst operating conditions.

High-performance, low-latency TCAMs are critical for packet classification at wire speeds. TCAM compilers include features such as hardened priority encoders, multiple options to lower power, and column redundancy for higher yield. TCAM IP includes multi-width search mode to switch dynamically between IPv4 and IPv6 searches. eSilicon also offers built-in self-test (BIST) and built-in self-repair (BISR) for high test coverage during wafer sort and production. The 16nm TCAM architecture has been advanced to include proprietary ECC architecture for today’s networking applications.

eSilicon’s patented Duo architecture achieves densities equivalent to the TCAMs that are configured of wider bit widths and the architecture does not compromise performance; it reduces leakage by as much as 0.66x and compare power by as much as 0.62x.

14/16nm Register Files and SRAMs

eSilicon’s fast cache offers speeds that exceed 2.5GHz under worst case operating conditions, while the dual-port SRAM offers an excess of 1.5Ghz. The dual-port SRAM supports two independent read and write ports, and plays a critical role in increasing system bandwidth by supporting parallel operations. These memories provide zero clock latency overhead, deterministic timing (versus RTL/synthesis-based solutions) and easily integrate on chip with existing design flows.

A variety of multi-port asynchronous and synchronous register files are available including pseudo architectures that provide multi-port functionality while significantly improving density.

PPA-Optimized Memory IP

Our memories are optimized across the spectrum of performance, power, area, and yield to address customer-specific market requirements. eSilicon memories support industry-standard EDA flows. We work closely with our foundry and integrated device manufacturer (IDM) partners to incorporate the latest guidelines, including statistical analysis, design for manufacturability (DFM) rules, and redundancy guidelines. We collaborate with our customers to customize an already-developed memory compiler or instance and optimize the functionality, performance, power, area, or yield to match their SoC’s design-specific needs.


Silicon-proven design kits are now available in 14nm and 16nm technologies.

Product Name Front-end Design Kit Back-end Design Kit Silicon Report
High-Speed SP TCAM Available Available Available
Ultra-High-Speed SP TCAM Available Available Available
High-Speed SP Fast Cache Available Available Available
High-Speed DP SRAM Available Available Available
High-Speed Pseudo 2-Port SRAM Available Available Available
High-Density Pseudo 2-Port SRAM Available Available Available
High-Density 2-Port Asynchronous RF Available Available Available
Ultra-High-Speed Pseudo 2-Port SRAM Available Available Available
High-Speed Four-Port Register File Available Available October 2017
1.8V Oxide 1.8V/2.5V/3.3V General-Purpose I/O Library Available Available Available
1.8V Oxide 1.8V LVDSOUT I/O Library Available Available Available
1024bit HBM2 PHY Available Available Available

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