eSilicon offers a set of high-performance and high-bandwidth IP and 2.5D solutions on 7nm technology that target networking and high-performance computing applications by offering 3.3GHz caches and TCAMs with up to 1.8 billion searches per second (worst-case operation), along with the 2.5D integration of up to 1228 Gbytes/sec data rate high-bandwidth memory (HBM2).
The 7nm IP platform is eSilicon’s second-generation platform, with architectural enhancements from our silicon-proven platform in previous FinFET technologies. It was designed specifically to meet the high-speed and high-bandwidth requirements of ASICs and ASSPs targeted for networking and high-performance computing applications. The platform includes the following IP:
Memory processing tends to be the bottleneck in network performance. If memory can’t keep up with increasingly fast processors, the processors have to wait, stalling the system. Specialty memories address the problem in a variety of ways. Ternary content-addressable memories (TCAMs) are unique: they search an entire lookup table in one cycle. eSilicon’s eFlexCAM™ TCAM compiler provides up to 2.5 billion search results in one second (GSPS) under typical operating conditions, enabling high-efficiency, cost-effective solutions for applications such as network search engines, cache for network processors, QoS services, classifications, Ethernet, ATM switches and other diverse networking applications.
User-selectable features include priority encoder, redundancy and bit-write options.
Patented Duo architecture may be licensed for reduced area and power savings for bit widths less than or equal to 80 bits.
High-bandwidth memory (HBM2) achieves higher bandwidth while consuming less power in a substantially smaller form factor than DDR4, or GDDR5. HBM2 technology addresses the bandwidth gap with up to 1228 Gbytes/sec data rate with four HBM2 stacks in a package. HBM2 has eight independent channels using a total of 1024 input and output pins. This density of signals, coupled with interposer design, requires careful design and thorough timing analysis. eSilicon has extensive experience in HBM2 systems, including IP design, systems in package (SiP) design, manufacturing, assembly and test.
The HBM2 PHY supports HBM2 based on the JEDEC JESD 235A standard. The PHY supports up to 307Gbytes/sec bandwidth with 8x128b channels at 2.4Gbps per I/O. The PHY is DFI 4.0 compliant with several controller-independent features such as:
eSilicon’s 7nm memories provide system-on-chip (SoC) architects with a reliable, affordable method of optimizing their product design. eSilicon optimizes its networking-centric memory compilers by leveraging ASIC system-level requirements for high bandwidth for optimal power, performance or area.
Our IP team has been a leading provider of high-quality memory IP since 2000. Our memories are available in 7nm-250nm technologies, optimized to meet challenging PPA requirements for leading foundry and integrated device manufacturer (IDM) processes.
Please contact eSilicon at email@example.com for more information, silicon quality results, white papers or data sheets.
All eSilicon IP is available in IP Navigator at https://star.esilicon.com, our online IP exploration tool. Navigator provides access to eSilicon’s full portfolio of IP products. Memory instances may be generated, analyzed and downloaded. Power, performance, and area (PPA) data is pre-loaded for easy data comparison and analysis.
Our HBM2 webinars and white paper, co-authored with SK Hynix, Amkor Technology, Northwest Logic and Avery Design Systems, are available at our Start Your HBM2/2.5D Design Today web page.
You may also be interested in our Advanced ASIC Video Series: